Improvement in fine structures has been continuing for improving integration density and also improving processing speed of a silicon semiconductor integrated circuit. Gate length of the MOS transistor has been shortened in combination with further improvement in fine structure. When the gate length is 65 nm or less, expectation for improvement of performance with a fine structure has been accompanied by limitations.
A strain transistor for improving mobility of carriers by creating a strain is a technology for realizing improvement in performance of the MOS transistor. Strain is generated by impressing stress to a channel region of a MOS transistor. ON-current is improved by raising mobility of electrons and holes.
An n-channel MOS transistor can improve mobility of electrons when a tensile stress is impressed to the channel region thereof A p-channel MOS transistor can improve mobility of holes when a compressed stress is impressed to the channel region thereof.
In the case of a PMOS transistor, when a source/drain region is formed with a silicon-germanium (SiGe) mixed crystal having a lattice constant larger than that of the Si substrate, a compressed stress is applied to the Si crystal of the channel region and thereby mobility of hole increases.
In the case of NMOS transistor, when the source/drain region is formed with a silicon-carbon (SiC) mixed crystal having the lattice constant smaller than that of the Si substrate, a tensile stress is applied to the Si crystal of the channel region and thereby mobility of electrons increases.
When the Si—Ge crystal is formed with the epitaxial growth on the Si substrate, thickness of the epitaxial layer which can be grown without misfit dislocation is limited to the thickness called the critical film thickness.